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Application Note 9966
generate 1-4 narrowband carriers or 1-2 wideband carriers.
Consult the ISL5217 documentation for detailed information
on using the ISL5217 evaluation board.
To connect the two boards together, J4 on the ISL5217eval
(DUC) is connected to J1 on the ISL5x61eval (DAC) via a
2x20 pin ribbon cable. The DAC board is configured as is
stocked, except R16 is not populated. See Figure 2 for a
block diagram of the two boards connected.
If a clock source is available that has both CLK and CLK, the
clocking of the two boards is simplified. CLK should connect
to the DUC evaluation board at J 11, with a T-connector that
has a 50 ? terminator attached. CLK should go to the DAC
evaluation board at J2 and also use a T-connector with a
50 ? terminator. (Or, 50 ? terminators can be populated on
the evaluation boards. See the board schematics for more
information on doing this.)
If a generator with CLK and CLK is not available, a single
clock source can be used. Connect a T-connector to J2 of
the DAC board and another to J11 of the DUC board.
Connect a DC-biased clock signal to the connector at J2,
then connect J2 and J11 together with a short cable.
Connect a 50 ? terminator to the other side of the
T-connector at J11 on the DUC board. Sometimes the length
of the clock cable running from the DAC board to the DUC
board has to be adjusted to achieve adequate setup and
hold times between DATA and CLK.
CLOCK (104M MAX)
RIBBON CABLE
CLOCK (104M MAX)
50 ?
SMA
CABLE
14 BITS
TO SPECTRUM
ANALYZER
ISL5x61
DAC
ISL5217
4CH DIGITAL
UP CONVERTER
ISL5x61 EVALUATION BOARD
+3.3V (<0.1A)
+5V (<2A)
ISL5217 EVALUATION BOARD
POWER
POWER
SUPPLY
SUPPLY
FIGURE 2. INTERSIL ISL5x61 + ISL5217 SETUP BLOCK DIAGRAM
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable.
However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its
use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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